This invention relates to a variable delay circuit having particular application in a read channel for a data storage device and, more particularly, to a delayed read data single shot (DRDSS) circuit that imparts a variable delay to a data signal read from different zones on a data storage device.
It is conventional in reading data from a magnetic medium, such as the read channel of a hard disk drive, to sense a flux change during a recurring predetermined "window." If a flux change is present during that window, a "1" is assumed to be present and if no flux change is present, a "0" is assumed. A series of "1"s and "0"s are recorded as a succession of alternating flux changes. That is, a positive-going (or negative-going) flux change is recorded to represent a "1", and no flux change represents a "0". Usually, a flux change that is opposite in polarity to the previous flux change is recorded to represent a "1", even if the successive flux changes are separated by several "0"s. This is intended to minimize interbit interference, noise and phase shifts which could result in an erroneous interpretation of a detected flux change. For example, if successive bits are thought of as occupying respective bit cells (also referred to as data cells), the flux change which is expected during a particular bit cell may be sufficiently shifted, or time-delayed, as to be detected during the next-following bit cell; thus giving rise to erroneous detections.
Data generally is recorded in self-clocking codes which are used, during a read operation, to provide synchronization for the window generator which thereby produces the proper detection window during which flux changes are sensed. A data separator normally is provided in the read channel to recover the timing information inherent in the self-clocking coded data reproduced from the magnetic medium and to use this timing information to generate a read clock. It is common to employ a phase-locked loop (PLL) to generate this read clock and to separate, or synchronize, the data pulses read from the medium with this read clock. The synchronized data pulses then are compared to the aforementioned window to determine if a "1" or "0" is present in a bit cell.
However, a data separator, or synchronizer, cannot operate instantaneously. That is, the PLL of the data separator cannot operate in real time so as to follow instantaneously the shifts and jitter normally experienced in the data pulses as those pulses are reproduced from the storage medium. Consequently, to provide accurate data separation, that is, to determine if the reproduced data pulse falls within the window generated during a bit cell, it is common to delay the data pulse before it is compared to the window. Stated otherwise, the data pulse is delayed before being supplied to the PLL from which the window is generated. Typically, the delay imparted to the data pulse is on the order of one-half of a bit cell; and the delay circuit which is used to produce this delay has been described by those of ordinary skill in the art as a one-half cell delay, an anticipator, a variable bit cell delay, a one-third cell delay and a delayed read data single shot (DRDSS). This delay circuit is referred to herein as the DRDSS circuit, which is believed to be a more accurate description thereof.
Heretofore, the DRDSS circuit exhibited a fixed delay. This presented no difficulty because the recording schemes that had been used to record the data pulses relied upon a uniform, constant data clock, regardless of the particular track in which the data pulses were recorded. Typically, a data clock frequency was selected to record the data pulses with maximum bit density in the innermost track, and since the same data clock frequency was used to record data pulses in the outermost track, the latter were recorded with a much reduced bit density. To improve the recording density for disk media, a so-called constant bit density recording technique has been developed. In this technique, the disk medium is divided into several radial zones, with each zone having substantially the same bit density as all other zones. In the preferred implementation, the data clock frequency is increased from zone to zone in the radially outward direction. Thus, data recorded in the outermost zone exhibits a clock frequency that is greater than the data recorded in the innermost zone, and this maintains the same bit density from zone to zone.
When reproducing data that had been recorded in constant bit density format, the size, or duration, of a bit cell is smaller for the outermost zone than it is for the innermost zone. However, if the delay imparted to a reproduced data pulse by the DRDSS circuit remains constant, this delay is either too great for the data pulses reproduced from the outer zones or is too small for the data pulses reproduced from the inner zones. In either event, data pulse phase shifts attributed to the medium can create significant timing jitter in the data separator PLL, resulting in data errors. The phase detector normally included in the data separator may be subjected to noise in the event that a reproduced data pulse undergoes a large phase shift.
One proposal to adapt the data separator to the different clock frequencies used in zone bit recording, and thus to account for bit cells of different durations, is described in U.S. Pat. No. 4,894,734. There, the reproduced data pulse is supplied to an anticipator, or delay circuit, formed as a delay line having several taps. Depending upon the particular zone from which the data pulse is recovered, a corresponding tap of the anticipator is selected to provide the delayed data pulse. However, this proposal is generally unsatisfactory because the implementation of a multi-tap delay line is quite large and expensive. As the size of disk drive apparatus is reduced from generation to generation, there simply is no available capacity (or "real estate") to accommodate a multi-tap delay line. Moreover, this proposal contemplates a fixed delay for a given zone, even though the actual clock frequency that is recovered from that zone may differ from its nominal frequency. That is, thermal effects, age, drift and other inherent characteristics of the magnetic medium may result in an effective clock frequency of the reproduced data pulses that differs from the designed frequency. Consequently, the actual size of a bit cell may differ from the expected size and the delay provided at a particular tap thus may be too large or too small for that bit cell.